1. Field of the Invention
The present invention relates to a chip scale package (CSP) and, more particularly, to a substrate less chip scale package and a method of making the same.
2. Description of the Prior Art
Generally, a semiconductor package can be classified as one of several types, including a resin sealing package, a tape carrier package (TCP), a glass-sealing package, a metal sealing package, etc. Also, each type of package can be classified according to whether it uses insertion technology or surface mount technology (SMT) as its mounting method.
Typical types of packages using insertion technology include a dual in-line package (DIP), a pin grid array (PGA), etc. Typical surface mount packages include a quad flat package (QFP), a plastic leaded chip carrier (PLCC), a ceramic leadless chip carrier (CLCC), a ball grid array (BGA), a CSP etc.
Currently, because of miniaturization of electronic devices, semiconductor packages using surface mount technology are more widely used than insertion technology, because they can be more reliably mounted on printed circuit boards (PCB).
A conventional quad flat package (QFP) using surface mount technology will be described with reference to FIG. 1, which includes a schematic cross-sectional view of the structure of a typical QFP semiconductor package. This structure comprises a semiconductor chip 11 in which electronic circuits are integrated. The chip 11 is attached to a mounting board 15 by an epoxy 16. Bonding wires 13 electrically connect the semiconductor chip 11 to leads or output terminals 12. A resin molding package 14 encapsulates the semiconductor chip 11 and the other elements to protect them from the external environment including possible combustion and corrosion.
In the conventional QFP having this structure, signals to and from the semiconductor chip 11 are transmitted to and from the leads 12 through the bonding wires 13. The signals are to elements mounted, for example, on a printed circuit board or mother board via the leads 12, which are connected to the circuit board.
In the QFP, the number of pins in the package gradually increases with increased integration of the semiconductor chip 11. However, there are physical limitations on the amount the distance between pins can be reduced. As a result, the package must be made large enough to accomodate the required number of pins. Given the recent trend toward miniaturization and high density of semiconductor devices, the resulting higher pin count calls for larger and larger package sizes, thus tending to defeat the purpose of achieving smaller devices.
Ball grid array (BGA) packages and chip scale packages (CSP) have been suggested to solve the problem. The BGA and CSP packages use a solder ball placed on one side of the semiconductor package as an input and output means and forms a package the same size as the semiconductor chip, which makes the package light, thin, simple and small. The CSP package has applicability in many areas.
FIG. 2 illustrates the structure of a BGA-type CSP comprising circuit patterns 25a formed on both sides thereof. The circuit substrate 25 is shown coated with solder masks 25b for protecting the circuit patterns 25a. A semiconductor chip 21 is attached on the center of the circuit substrate 25. Wires 23 electrically connect the semiconductor chip 21 to the circuit patterns 25a of the circuit substrate 25 and transfer signals therebetween. Solder balls 22 serve as the output terminals fused on the circuit patterns 25a of the circuit substrate 25 to the signals in and out of the circuit. A resin package encapsulating the semiconductor chip 21 and its peripherals protects them from the external environment.
In the CSP structure, signals from the semiconductor chip 21 are transmitted to the substrate 25 via the wires 23. The signals pass through the circuit patterns 25a in the back side and are transmitted to the peripheral elements through the solder balls 22 which are the output terminals. Signals from the peripheral elements are transmitted to the semiconductor chip 11 in reverse fashion.
As described above, the conventional CSP fixes the semiconductor chip 21 by using the substrate 25 as a PCB or a ceramic substrate. The front side of the substrate 25 and the semiconductor chip are connected by the wires 23, and the back side of the substrate 25 and the output terminals of the package are connected by the circuit patterns 25a. This type of structure has certain drawbacks including long interconnection delays in the time of transmitting signals. Also, it is difficult to accurately achieve certain device performance characteristics since the circuit patterns 25a are formed on the front and back side of the substrate 25 and are connected to each other.
Also, it is difficult to produce a highly reliable CSP because of the adhesive force between a conventional PCB used as a substrate and the resin package, the difference of coefficient of thermal expansion between them, the flaking of the resin package over temperature ranges and cracking occurring due to introduction of moisture into the substrate.
It is one object of the present invention to provide a chip scale package (CSP) in which a semiconductor chip is connected directly to output terminals of the package without a substrate to reduce the length of interconnection, to miniaturize the package and to remove the defects generated by a substrate.
It is another object of the present invention to provide a method of making a CSP having no substrate.
In one aspect, the present invention is directed to a substrateless chip scale package. Electronic circuits of the device are integrated on a semiconductor chip in the package. The chip includes one or more bonding pads on its upper side. A plurality of output terminals are disposed around an edge of a lower side of the semiconductor chip in a plane which is below the lower side of the semiconductor chip. A plurality of bonding wires electrically connect a plurality of the bonding pads with corresponding output terminals of the device. A molded material encapsulates the bonding wires and associated elements and does not encapsulate a central portion of the lower side of the semiconductor chip and the lower side of a plurality of the output terminals.
In another aspect, the present invention is directed to a method for providing a chip scale package having no substrate. In accordance with this aspect, several output terminals are arranged on a tape film. A semiconductor chip having circuits integrated therein is attached and fixed on the center of the tape film, on which output terminals are arranged using a bonding means attached on the same level with the output terminals. Bonding pads formed on the upper side of the semiconductor chip are electrically connected to the output terminals by bonding wires. A molded material is formed to at least partially encapsulate the bonding wires. The output means is exposed by removing the tape film and the bonding means.
In one embodiment, the output terminals are made of a conductive metal which can be copper (Cu), gold (Au), titanium (Ti), palladium (Pd), silver (Ag) or an alloy thereof. The tape film can be made of a sheet-type metal foil or polyimide. The bonding means can be made of a silver paste, a bonding agent of sheet-type silicon or an elastomer.